`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:01:08 04/20/2011 
// Design Name: 
// Module Name:    HazardDetectionUnit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
	module HazardDetectionUnit(IDEX_MemRead, IDEX_Rt, IFID_Rs, IDEX_Rt, IFID_Rt,
	stall, PCWrite);

	input IDEX_MemRead;
	input [3:0] IDEX_Rt;
	input [3:0] IFID_Rs;
	input [3:0] IDEX_Rt;
	input [3:0] IFID_Rt;
	output stall;
	output PCWrite;
	
	reg stall;
	
	always @ (*)
	begin
		if (IDEX_MemRead && ((IDEX_Rt == IFID_Rs) || (IDEX_Rt == IFID_Rt)))
			begin
			stall <= 1'b1;
			PCWrite <= 1'b0;
			end
		else
			begin
			stall <= 1'b0;
			PCWrite <= 1'b1;
			end
	end


endmodule
